module cond(
    /*AUTOARG*/
   // Outputs
   cnd,
   // Inputs
   ifun, cc
   );

input [3:0] ifun; 
input [2:0] cc; 
output cnd; 

wire zf = cc[2]; 
wire sf = cc[1]; 
wire of = cc[0]; 

// Reference pipe.v
assign cnd = 
    (ifun == `C_YES) | // all 
    (ifun == `C_LE & ((sf^of)|zf)) | // <= 
    (ifun == `C_L & (sf^of)) | // < 
    (ifun == `C_E & zf) | // == 
    (ifun == `C_NE & ~zf) | // != 
    (ifun == `C_GE & (~sf^of)) | // >= 
    (ifun == `C_G & (~sf^of)&~zf); // >

endmodule 
